1. Field of the Invention
The present invention relates to a bipolar transistor used for forming an integrated circuit, particularly, to a bipolar transistor achieving an excellent high speed performance and operable with a small power consumption.
2. Description of the Related Art
Recently, various constructions have been proposed with respect to a bipolar transistor used for forming an integrated circuit in an attempt to provide a transistor capable of a high speed performance and operable with a small power consumption. For example, Japanese Patent Disclosure 56-80161 teaches a planar type bipolar transistor constructed as shown in FIG. 1A. This transistor, in which an emitter region 1, a base region 2 and a collector region 3 are formed by self-alignment, is featured as follows:
(1) The emitter/base junction is very small and is basically flat;
(2) The base/collector junction is basically flat and is roughly equal to the emitter/base junction in size;
(3) The emitter region 1, base region 2 and collector region 3 are surrounded by a polysilicon region 4 of a high conductivity; and
(4) The polysilicon region 4 is electrically insulated from the emitter region 1 by a first insulating region 5 and from the collector region 3 by a second insulating region 6. The polysilicon region 4 also acts as a side contact for the active base region 2 and as a base contact for a metal electrode.
A bipolar transistor constructed as shown in FIG. 1B is disclosed in a literature "Flat Emitter Transistor with Self-Aligned Base" by Fujita et al, which was announced in "International Solid-State Circuits Conference, 1980" and published in "Jap. J. of Appl. Phys. vol. 20, Suppl. 20-1, pp 149-153". This transistor is featured in that the emitter/base junction is substantially flat. Also, the p-type impurity concentration in the outer base region 4 is as high as very close to the impurity concentration in the emitter region 1, leading to a low base resistance.
Further, a bipolar transistor constructed as shown in FIG. 1C is disclosed in a literature "Self-Aligned Transistor with Sidewall Base Electrode" by Nakamura et al., which was announced in "International Solid-State Circuits Conference, 1980". This transistor is featured as follows:
(1) The base/collector junction and a part of the side wall of the collector region 3 are surrounded by an insulating region 6;
(2) A polysilicon region 4 is formed on the insulating region 6 to achieve electric connection of the base region 2;
(3) The impurity in the polysilicon region 4 is diffused into a part of the collector region 3 to form an outer base region between the polysilicon region 4 and the base region 2; and
(4) The outer base region is in contact with the emitter region 1 at a side part of the emitter region 1.
The conventional basic idea for enabling a bipolar transistor to achieve a high speed performance and to operate with a small power consumption is to form the p-n junction shallow in the vertical direction and to diminish the size in the horizontal direction. The transistors shown in FIGS. 1A to 1C are based on this basic idea.
The conventional theoretic study on the operation speed of a vertical bipolar transistor is based on a one dimensional model, on the assumption that the operation speed is determined by the carrier moving speed in the vertical direction. Each of the transistors shown in FIGS. 1A to 1C is based on this one dimensional model.
It has been found, however, as a result of the research made by the present inventor using a computer simulation that, in the case of a large signal amplitude, the operation speed of a bipolar transistor is determined by a factor which is not included in the one dimensional model. To be more specific, a base-widening region is formed in the collector region during operation of a bipolar transistor. What should be noted is that the carrier is charged and discharged in the two dimensional direction, i.e., both in the vertical and horizontal directions, in the base-widening region. The operation speed of the transistor is determined by the charging and discharging in the two dimensional direction in the case of a large signal amplitude.
The carriers injected through the outer base region, i.e., holes in the example of FIG. 1, are accumulated in the inner base region, leading to the "base-widening" noted above. Specifically, the carriers thus accumulated overflow the inner base region, with the result that the region substantially acting as a base is expanded into a part of the collector region. Of course, the "base-widening region" denotes the region positioned within the collector region and substantially acting as the base.
Each of the transistors shown in FIGS. 1A to 1C leaves room for further improvement in its operation speed in view of the fact that the charging and discharging in the two dimensional direction within the base-widening region is deeply related to the operation speed of a transistor. As pointed out previously, these transistors are designed on the basis of a one dimensional model, with the result that the charging and discharging speed of the carrier in, particularly, the horizontal direction is insufficient in the base-widening region. For example, the transistor shown in FIG. 1A does not include an outer base region which is in ohmic contact with the base-widening region formed in the collector region 3. It follows that the holes in the base-widening region are not directly released into the outer base region, making it necessary for the holes to be released through a bypath of a high resistance leading from the inner base region 2 to the outer base region. Naturally, the discharging takes time to obstruct the high speed operation of the transistor.
In the transistors shown in FIGS. 1B and 1C, the base-widening region is in direct contact with the outer base region 4. In these cases, however, the impurity concentration profile in the outer base region 4 is not adapted to permit the holes in the base-widening region to be released directly into the outer base region. It follows that the discharging takes time to obstruct the high speed operation of the transistor, as in the transistor shown in FIG. 1A.